CXMT's new DRAM tech to test Korean memory makers' dominance

CXMT plans to launch a server DDR5 product in Shanghai by the end of this year using a 4F square memory-cell architecture. The design could reduce cell area by 33 percent and fit 50 percent more cells into the same space, challenging Korean memory makers whose adoption plans remain on technology road maps. Samsung Electronics and SK hynix shares fell 7.39 percent and 10.09 percent, respectively, after the announcement, though industry officials said production yields, customer qualification and actual shipments remain unconfirmed.

The current industry standard is a 6F square cell, while 4F square means each cell occupies an area equivalent to four times the minimum line width squared.

Samsung Electronics reportedly identified a working die based on 4F square architecture while developing sub-10-nanometer DRAM through its 10a process, but it has not officially announced a production timeline.

SK hynix outlined plans for a 4F square platform for sub-10-nanometer DRAM in a technology road map unveiled in Japan last year, without disclosing a mass-production schedule.

CXMT has been producing DRAM with a roughly 16-nanometer process and faces restrictions on obtaining extreme ultraviolet lithography equipment.

CXMT said its proprietary Vertical Surrounded Gate transistor architecture is intended to reduce memory-cell size and increase storage density.

Published Oct 13, 2026 4:18 pm KST

Questions remain over Chinese memory giant's technological leap

A CXMT wafer is displayed at World Manufacturing Convention 2026 in Hefei, China, Sept. 23. Yonhap

Concerns are growing that the technological gap between China's CXMT and Korean memory makers Samsung Electronics and SK hynix in DRAM technology has already narrowed, after the Chinese company unveiled plans to launch server memory product by the end of this year featuring a next-generation memory cell architecture that remains only on the technology road maps of the two Korean chipmakers.

According to South China Morning Post and other Chinese media outlets, CXMT President Cao Kanyu said the company plans to roll out a new server DDR5 based featuring the new architecture during an industrial event in Shanghai on Saturday.

The new architecture uses a design called 4F square, which reduces the space occupied by each memory cell. F refers to the minimum line width that a given DRAM manufacturing process can draw. In current processes such as 1a, 1b and 1c, F is just over 10 nanometers. 4F square means each cell occupies an area equivalent to four times F squared.

The current industry standard is 6F square, meaning the new technology could theoretically reduce the area occupied by each memory cell by 33 percent and allow 50 percent more cells to fit into the same space, increasing the amount of data that can be stored on a chip.

Shrinking memory cells requires technological breakthroughs, such as arranging transistors vertically rather than horizontally. Samsung Electronics and SK hynix have been developing technologies such as Vertical Channel Transistors, but their plans to adopt the new cell architecture remain on their technology road maps.

In April, reports claimed that Samsung Electronics identified a working die based on 4F square cell architecture while developing sub-10-nanometer DRAM using process called 10a. Industry observers expect the company may begin 4F square DRAM production in 2028, but Samsung has yet to officially announce a timeline.

SK hynix also unveiled a technology road map in Japan in June last year outlining plans to introduce a 4F square platform for sub-10-nanometer DRAM, but has not disclosed a mass production schedule.

Against this backdrop, CXMT said it is working to reduce memory cell size and increase storage density using its proprietary Vertical Surrounded Gate transistor architecture.

A screen displays KOSPI and stock prices of Samsung Electronics and SK hynix at Woori Bank headquarters in Seoul, Tuesday. Yonhap

Although details regarding mass production, customer qualification, yields and shipment volumes remain unconfirmed, the announcement has fueled concerns that China's technological advances in DRAM could extend from consumer memory products to higher-value server DRAM.

Shares of global memory makers, including Micron Technology and Sandisk, reacted to the news on Monday, followed by Samsung Electronics and SK hynix, whose shares fell 7.39 percent and 10.09 percent, respectively, on Tuesday.

Though the announcement affected share prices in the market which has become increasingly sensitive to semiconductor-related news, industry officials largely agree that it is too early to assess the implications.

“There is a difference between announcing plans to launch a product and actually bringing it to market,” an industry official said. “We need to look at productivity, production yields, which customers will buy the products and whether they have passed customer qualification. These are the factors that will ultimately determine whether CXMT can translate its technology into actual sales.”

Samsung Electronics HBM4, a sixth-generation high-bandwidth memory solution for artificial intelligence and high-performance computing applications, on display during the 2025 Korea Tech Festival in Seoul, Dec. 4, 2025. Reuters-Yonhap

Technical questions are also emerging. Until recently, CXMT had been producing DRAM using a roughly 16-nanometer process, equivalent to the 1y to 1z generations. While the company seeks to advance to finer processes such as 1a, 1b and 1c, U.S.-led export restrictions have prevented it from obtaining extreme ultraviolet lithography equipment.

This raises questions about how much CXMT can actually reduce memory cell size by switching from a 6F square to a 4F square architecture while its minimum feature size, F, remains relatively large.

Industry observers say Samsung Electronics and SK hynix's plans to adopt 4F square architectures only at sub-10-nanometer process nodes also reflect considerations of cost-effectiveness and production efficiency. From this perspective, CXMT's transition to 4F square could be seen as an alternative approach to reducing cell size when further process miniaturization remains difficult.

“Major memory chipmakers are capable of producing working samples at the R&D stage, but they do not make aggressive announcements because those samples are not commercial products,” another industry official said.

“CXMT appears to have made an aggressive announcement to impress the market following its recent initial public offering. With the entire memory market facing supply shortages, there is still room for companies like CXMT to gain ground in commodity memory products. But I have not heard of CXMT or YMTC securing any major orders in the data center or server markets. I think the market is reacting too sensitively, and it is still too early to say that the technology gap has completely closed.”

CXMT计划于今年年底前在上海推出一款采用4F方形内存单元架构的服务器DDR5产品。该设计可将单元面积减少33%，并在相同空间内容纳多50%的单元，这对韩国内存制造商构成了挑战，因为他们的采用计划仍停留在技术路线图上。消息公布后，三星电子和SK海力士的股价分别下跌了7.39%和10.09%，但业内人士表示，生产良率、客户认证和实际出货量仍有待确认。

目前的行业标准是 6F 正方形单元格，而 4F 正方形表示每个单元格占据的面积相当于最小线宽平方的四倍。

据报道，三星电子在通过其 10a 工艺开发 10 纳米以下 DRAM 时，已经确定了一种基于 4F 方形架构的可用芯片，但尚未正式宣布量产时间表。

SK 海力士去年在日本发布的技术路线图中概述了用于 10 纳米以下 DRAM 的 4F 方形平台计划，但没有透露量产时间表。

CXMT 一直采用大约 16 纳米工艺生产 DRAM，但在获取极紫外光刻设备方面面临限制。

CXMT表示，其专有的垂直环绕栅极晶体管架构旨在减小存储单元尺寸并提高存储密度。

发布于2026年10月13日下午4:18（韩国标准时间）

中国存储巨头的技术飞跃仍存在诸多疑问。

9月23日，在2026年世界制造业大会（World Manufacturing Convention 2026）上，CXMT晶圆亮相于中国合肥。（韩联社）

在中国公司CXMT宣布计划在今年年底前推出服务器内存产品后，人们越来越担心中国CXMT与韩国内存制造商三星电子和SK海力士在DRAM技术方面的技术差距已经缩小。CXMT的产品采用了下一代内存单元架构，而这种架构目前仅存在于这两家韩国芯片制造商的技术路线图上。

据《南华早报》等中国媒体报道，CXMT总裁曹侃宇表示，公司计划于周六在上海举行的一场行业活动中推出一款基于DDR5、采用全新架构的服务器。

新架构采用了一种名为 4F 平方的设计，可以减少每个存储单元占用的空间。F 指的是特定 DRAM 制造工艺所能绘制的最小线宽。在目前的工艺（例如 1a、1b 和 1c）中，F 略大于 10 纳米。4F 平方意味着每个单元占用的面积相当于 F 的四倍。

目前的行业标准是 6F 平方，这意味着新技术理论上可以将每个存储单元占用的面积减少 33%，并允许在相同的空间内容纳多 50% 的单元，从而增加芯片上可以存储的数据量。

缩小存储单元尺寸需要技术突破，例如将晶体管垂直排列而非水平排列。三星电子和SK海力士一直在开发垂直通道晶体管等技术，但它们采用这种新型单元架构的计划仍停留在各自的技术路线图上。

今年4月有报道称，三星电子在采用名为10a的工艺开发10纳米以下DRAM时，发现了一种基于4F方形单元架构的可用芯片。业内人士预计，该公司可能在2028年开始量产4F方形DRAM，但三星尚未正式公布时间表。

SK 海力士去年 6 月在日本公布了一项技术路线图，概述了推出 4F 方形平台用于 10 纳米以下 DRAM 的计划，但尚未公布量产计划。

在此背景下，CXMT表示，它正致力于利用其专有的垂直环绕栅极晶体管架构来减小存储单元尺寸并提高存储密度。

周二，首尔友利银行总部的大屏幕上显示着韩国综合股价指数（KOSPI）以及三星电子和SK海力士的股票价格。（韩联社）

尽管有关大规模生产、客户资质、良率和出货量等细节仍未得到证实，但该公告引发了人们的担忧，即中国在DRAM领域的技术进步可能会从消费级内存产品扩展到更高价值的服务器DRAM。

周一，包括美光科技和闪迪在内的全球存储器制造商的股价对这一消息做出反应，随后三星电子和SK海力士的股价周二分别下跌了7.39%和10.09%。

尽管该消息影响了对半导体相关新闻越来越敏感的市场股价，但业内人士普遍认为，现在评估其影响还为时过早。

一位业内人士表示：“宣布产品上市计划和真正将其推向市场是两回事。我们需要考虑生产效率、产量、哪些客户会购买这些产品，以及他们是否通过了客户资质认证。这些因素最终将决定CXMT能否将其技术转化为实际销售额。”

三星电子第六代高带宽内存解决方案HBM4于2025年12月4日在首尔举行的2025年韩国科技节上展出，该方案专为人工智能和高性能计算应用而设计。（路透社-韩联社）

技术问题也随之出现。直到最近，CXMT 一直采用大约 16 纳米的工艺生产 DRAM，相当于 1y 到 1z 代工艺。虽然该公司寻求推进到更精细的工艺，例如 1a、1b 和 1c 代，但美国主导的出口限制使其无法获得极紫外光刻设备。

这就引出了一个问题：CXMT 通过将 6F 方形架构切换到 4F 方形架构，在最小特征尺寸 F 仍然相对较大的情况下，究竟能将存储单元尺寸缩小多少？

业内人士指出，三星电子和SK海力士计划仅在10纳米以下的工艺节点上采用4F方形架构，也体现了对成本效益和生产效率的考量。从这个角度来看，CXMT向4F方形架构的过渡可以被视为在工艺进一步小型化仍然困难的情况下，缩小单元尺寸的一种替代方案。

另一位业内人士表示：“主要的存储芯片制造商有能力在研发阶段生产出可用的样品，但他们不会大张旗鼓地进行宣传，因为这些样品并非商业产品。”

“CXMT似乎在近期完成首次公开募股后，发布了一项激进的公告以期给市场留下深刻印象。鉴于整个内存市场面临供应短缺，像CXMT这样的公司在通用内存产品领域仍有发展空间。但我尚未听说CXMT或YMTC在数据中心或服务器市场获得任何重大订单。我认为市场反应过于敏感，现在就断言技术差距已经完全消除还为时过早。”